Structured low-density parity-check (LDPC) code

ABSTRACT

A method for constructing a low-density parity-check (LDPC) code using a structured base parity check matrix with permutation matrix, pseudo-permutation matrix, or zero matrix as constituent sub-matrices; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for constructing a LDPC code using a structured base parity check matrix H=[H d |H p ], H d  is the data portion, and H p  is the parity portion of the parity check matrix; the parity portion of the structured base parity check matrix is such so that when expanded, an inverse of the parity portion of the expanded parity check matrix is sparse; and expanding the structured base parity check matrix into an expanded parity check matrix. A method for encoding variable sized data by using the expanded LDPC code; and applying shortening, puncturing.System and method for operating a wireless device to encode data using low-density parity-check (LDPC) encoding is discussed. One example method includes: computing a number of modulated orthogonal frequency-division multiplexing (OFDM) symbols for transmitting the data; computing a number of shortening bits; distributing the number of shortening bits over the at least one LDPC codeword; computing a number of puncturing bits for the at least one LDPC codeword; distributing the number of puncturing bits over the at least one LDPC codeword; determining a criterion using at least one of the number of shortening bits and the number of puncturing bits; if the criterion is met, increasing the number of modulated OFDM symbols and recalculating the number of puncturing bits; generating the encoded data using the number of shortening bits, the number of puncturing bits, and the at least one LDPC codeword; and transmitting the encoded data.

This application is a continuation reissue application, which is areissue application of U.S. application Ser. No. 13/156,942, filed onJun. 9, 2011 and issued as U.S. Pat. No. 8,301,975 on Oct. 30, 2012 anda continuation of U.S. application Ser. No. 15/838,188, filed on Dec.11, 2017, which is a reissue application of U.S. application Ser. No.13/156,942, filed on Jun. 9, 2011 and issued as U.S. Pat. No. 8,301,975on Oct. 30, 2012 and a divisional of Ser. No. 14/527,483, filed Oct. 29,2014 and issued as U.S. Pat. No. RE46,692 on Jan. 30, 2018, which is areissue application of U.S. application Ser. No. 13/156,942, filed onJun. 9, 2011 and issued as U.S. Pat. No. 8,301,975 on Oct. 30, 2012,which is a continuation of U.S. application Ser. No. 11/665,171, filedon Jul. 29, 2008 and issued as U.S. Pat. No. 7,996,746 on Aug. 9, 2011,which is a National Stage Entry of PCT/CA2005/01563 filed on Oct. 12,2005, which claims the benefits of U.S. Provisional Applications No.60/635,525, filed Dec. 13, 2004; 60/617,902, filed Oct. 12, 2004;60/627,348, filed Nov. 12, 2004; 60/635,525, filed Dec. 13, 2004;60/638,832, filed Dec. 22, 2004; 60/639,420, filed Dec. 22 27, 2004;60/647,259, filed Jan. 26, 2005; 60/656,587, filed Feb. 25, 2005; and60/673,323, filed Apr. 20, 2005.

FIELD OF THE INVENTION

The present invention generally pertains to forward error correction. Inparticular, the present invention relates to structured Low-DensityParity-Check (LDPC) codes.

BACKGROUND OF THE INVENTION

In a typical communication system, forward error correction (FEC) isoften applied in order to improve robustness of the system against awide range of impairments of the communication channel.

Referring to FIG. 1, in which a typical communication network channel isdepicted having an information source 101, sending data to a sourcecoder 102 that in turn forwards the data to a channel encoder 103. Theencoded data is then modulated 104 onto a carrier before beingtransmitted over a channel 105. After transmission, a like series ofoperations takes place at the receiver using a demodulator 106, channeldecoder 107 and source decoder 108 to produce data suitable for theinformation sink 109. FEC is applied by encoding the information datastream at the transmit side at the encoder 103, and performing theinverse decoding operation on the receive side at the decoder 107.Encoding usually involves generation of redundant (parity) bits thatallow more reliable reconstruction of the information bits at thereceiver.

In many modern communication systems, FEC uses Low-Density Parity-Check(LDPC) codes that are applied to a block of information data of thefinite length.

One way to represent LDPC codes is by using so-called Tanner graphs, inwhich N symbol nodes, correspond to bits of the codeword, and M checknodes, correspond to the set of parity-check constraints which definethe code. Edges in the graph connect symbol nodes to check nodes.

LDPC codes can also be specified by a parity check matrix H of size M×N.In the matrix H, each column corresponds to one of the symbol nodeswhile each row corresponds to one of the check nodes. This matrixdefines an LDPC block code (N, K), where K is the information blocksize, N is the length of the codeword, and M is the number of paritycheck bits. M=N−K. A general characteristic of the LDPC parity checkmatrix is the low density of non-zero elements that allows utilizationof efficient decoding algorithms. The structure of the LDPC code paritycheck matrix is first outlined in the context of existing hardwarearchitectures that can exploit the properties of these parity checkmatrices.

In order to accommodate various larger code rates without redesigningparity check matrix and therefore avoiding changing significantly basehardware wiring, expansion of a base parity check matrix is one of thecommon approach. This may be archived, for example, by replacing eachnon-zero element by a permutation matrix of the size of the expansionfactor.

One problem often faced by the designer of LDPC codes is that the baseparity check matrices are designed to follow some assumed degreedistribution, which is defined as the distribution of column weights ofthe parity check matrix. Column weight in turn equals the number of in acolumn. It has been shown that irregular degree distributions offer thebest performance on the additive white Gaussian noise channel. However,the base parity check matrix does not exhibit any structure in its H_(d)portion to indicate the final matrix after expansion. The number ofsub-matrix blocks, corresponding to the number of sub-iterations in thelayered decoding algorithm may become large. Since the maximum number ofrows that can be processed in parallel equals the number of rows in thesub-matrix block, the overall throughput may be impacted.

Another problem is that in order to maintain the performance such ascoding gain as high as possible, there are different requirements suchas to select the largest suitable codeword from the available set ofcodewords and then properly adjust the amount of shortening andpuncturing; use as few of the modulated symbols as possible; and keepthe overall complexity at a reasonable level.

Some attempts have been made to enhance the throughput by reducing thenumber of rows of the base parity matrix, and consequently the number ofblock of rows in the expanded parity check matrix, by combining rows asa method to increase the code rate without changing the degreedistribution. However, the derived high rate matrix is still relativelylarge, since in order to allow row combining, the original low rate baseparity matrix usually has a large number of rows. The decoding time alsobecomes a function of the code rate: the higher the code rate the lesslayers in the layered decoding and, in general, less decoding time.

Other existing approaches for shortening and puncturing of the expandedmatrices may preserve the column weight distribution, but may severelydisturb the row weight distribution of the original matrix. This, inturn, causes degradation when common iterative decoding algorithms areused. This adverse effect strongly depends on the structure of theexpanded matrix.

Therefore, there is an unmet need for a method, a system to designstructured base parity check matrices, in combination with expansion,allow achieving high throughput, low latency, and at the same time, thepreservation of the simple encoding feature of the expanded codeword.

There is further an unmet need for a method and a system to enableflexible rate adjustments by using shortening, or puncturing, or acombination of shortening and puncturing; and at the same time the coderate is approximately the same as the original one, and the coding gainis preserved.

SUMMARY OF THE INVENTION

In accordance with a first aspect of the present invention there isprovided a method for constructing a low-density parity-check (LDPC)code having a structured parity check matrix comprising the steps of: a)constructing a structured base parity check matrix having a plurality ofsub-matrices, the sub-matrices are selected from a group consisting ofpermutation matrix, pseudo-permutation matrix, and zero matrix; and b)expanding the structured base parity check matrix into an expandedparity check matrix.

Preferably, the sub-matrices in the plurality of sub-matrices have thesame size.

Preferably, a majority of the plurality of sub-matrices has the samesize, and a small subset of the sub-matrices is constructed byconcatenating smaller permutation sub-matrices, pseudo-permutationmatrices or zero matrices.

Preferably, the method of claim 1 wherein the base parity check matrixis in the form of H=[H_(d)|H_(p)], H_(d) being a data portion of theparity check matrix, H_(p) being a parity portion of the parity checkmatrix.

Preferably, the expanding step further comprises the steps of: replacingeach non-zero member of the sub-matrices by a permutation matrix or apseudo-permutation matrix; and replacing each zero member of thesub-matrices by a zero matrix.

Preferably, the parity portion of the structured base parity checkmatrix comprises a dual diagonal.

In accordance with another aspect of the present invention there isprovided a method for decoding data stream encoded using the LDPC codecomprising the steps of: a) receiving a set of input valuescorresponding to variable nodes of the structured parity check matrix;and b) estimating a probability value of the variable nodes based on theplurality of parity checks contained within an block of parity checkscorresponding to a row of sub-matrices of the base parity check matrix,over the blocks of the base parity check matrix.

Preferably, the estimating step is repeated until a terminationcriterion is reached.

In accordance with another aspect of the present invention there isprovided a device for decoding data stream encoded using LDPC code,comprising: a) intra-layer storage elements for receiving a set of inputvalues corresponding to variable nodes of the structured parity checkmatrix, and for storing the updated variable nodes information; b) aread network for delivering the information from the intra-layer storageelements to the processing units; c) processing units for estimating aprobability value of the variable nodes based on a plurality of paritychecks contained within a block of parity checks corresponding to a rowof sub-matrices of the base parity check matrix; d) inter-layer storagefor storing additional information from sub-matrices concatenated usingsub-matrices selected from a group consisting of permutation matrix,pseudo-permutation matrix, and zero matrix; and d) a write network fordelivering the results from processing units to the intra-layer storageelements.

In accordance with another aspect of the present invention there isprovided a method for constructing a low-density parity-check (LDPC)code having a structured parity check matrix comprising the steps of: a)constructing a structured base parity check matrix H=[H_(d)|H_(p)],H_(d) being a data portion of the parity check matrix, H_(p) being aparity portion of the parity check matrix; b) selecting a parity portionof the structured base parity check matrix so that when expanded, aninverse of the parity portion of the expanded parity check matrix issparse; and c) expanding the structured base parity check matrix into anexpanded parity check matrix.

In accordance with another aspect of the present invention there isprovided a method for constructing a low-density parity-check (LDPC)code having a structured parity check matrix, the method comprising thesteps of: a) constructing a base parity check matrix H=[H_(d)|H_(p)]having a plurality of elements, H_(d) being a data portion of the paritycheck matrix, H_(p) being the parity portion of the parity check matrix;b) expanding the base parity check matrix into an expanded parity checkmatrix by replacing each non-zero element of the plurality of elementsby a shifted identity matrix, and each zero element of the plurality ofelements by a zero matrix; wherein the base parity check matrix has acoding rate selected from the group consisting of R=½, ⅔, ¾, ⅚, and ⅞;and accordingly is of the size selected from the group consisting of12×24, 8×24, 6×24, 4×24, and 3×24.

Preferably, the base parity check matrix has a coding rate of R=¾, andis:

1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 1 0 0 10 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 1 0 1 1 1 1 0 0 1 1 0 01 1 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 1.

More preferably, the base parity check matrix is expanded by expansionfactors L between 24 and L_(max)=96, and is represented by the expandedparity check matrix:

 6 38  3 93 −1 −1 −1 30 70 −1 86 −1 37 38  4 11 −1 45 48  0 −1 −1 −1 −162 94 19 84 −1 92 78 −1 15 −1 −1 92 −1 45 24 32 30 −1 −1  0  0 −1 −1 −171 −1 55 −1 12 66 45 79 −1 78 −1 −1 10 −1 22 55 70 82 −1 −1  0  0 −1 −138 61 −1 66  9 73 47 64 −1 39 61 43 −1 −1 −1 −1 95 32  0 −1 −1  0  0 −1−1 −1 −1 −1 32 52 35 80 95 22  6 51 24 90 44 20 −1 −1 −1 −1 −1 −1  0  0−1 63 31 88 20 −1 −1 −1  6 40 56 16 71 53 −1 −1 27 26 48 −1 −1 −1 −1  0wherein −1 represents L×L all-zero square matrix, the integer s_(ij)represents circular shifted L×L identity matrix, the amount of the shifts′_(ij) is determined as follows:

$s_{ij}^{\prime} = \left\{ \begin{matrix}{\text{floor}{\left( \frac{L \times s_{ij}}{L_{\max}} \right),}} & {s_{ij} > 0} \\{s_{ij},} & \text{otherwise.}\end{matrix} \right.$

In accordance with another aspect of the present invention there isprovided a method for encoding variable sized data using low-densityparity-check (LDPC) code and transporting the encoded variable sizeddata in modulated symbols, the method comprising the steps of: a)calculating a minimum number of modulated symbols capable fortransmitting a data packet; b) selecting an expanded parity check matrixhaving a proper codeword size suitable for transmitting the data packet;c) calculating a number of shortening Nshortened bits to be used duringtransmission of the data packet; and d) calculating a number ofpuncturing Npunctured bits to, be used during transmission of the datapacket.

Preferably, the method further comprises the steps of: a) constructingone or more than one structured base parity check matrixH=[H_(d)|H_(p)], H_(d) being a data portion of the parity check matrix,H_(p) being a parity portion of the parity check matrix; and b)expanding the one or more than one structured base parity check matrixinto one or more than one expanded parity check matrix, each of the oneor more than one expanded parity check matrix having a differentcodeword size for use in the selecting step.

Preferably, the method further comprises the steps of: a) determining aperformance criterion of the shortened and punctured expanded paritycheck matrix; b) adding an additional symbol to transmit the encodeddata packet in the case when performance criterion is not met; and c)recalculating the amount of puncturing N_(punctured) bits.

Preferably, the method further comprises the steps of: a) selectingN_(shortened) variable nodes from the expanded parity check matrix; b)ensuring a uniform or a close to uniform row weight distribution afterremoving columns corresponding to the selected N_(shortened) variablenodes; and c) ensuring a new column weight distribution as close aspossible to an original column weight distribution after removing thecolumns corresponded to the selected N_(shortened) variable nodes fromthe selected expanded parity check matrix.

Preferably, the selecting N_(shortened) variable nodes step furthercomprises the step of selecting variable nodes belonging to consecutivecolumns in the selected expanded parity check matrix.

Preferably, the ensuring a new column weight distribution step furthercomprises the step of prearranging columns of the data portion Hd of theselected expanded parity check matrix.

Preferably, the method further comprises the steps of: a) determining aperformance criterion of the shortened and punctured expanded paritycheck matrix; b) adding an additional symbol to transmit the encodeddata packet in the case when the performance criterion is not met; andc) recalculating the amount of puncturing N_(punctured) bits.

Preferably, the method further comprises the steps of a) selectingN_(shortened) variable nodes from the expanded parity check matrix; b)ensuring a uniform or a close to uniform row weight distribution afterremoving columns corresponding to the selected N_(shortened) variablenodes; and c) ensuring a new column weight distribution as close aspossible to an original column weight distribution after removing thecolumns corresponded to the selected N_(shortened) variable nodes fromthe selected expanded parity check matrix.

More preferably, the selecting step further comprises the step ofselecting variable nodes belonging to consecutive columns in theselected expanded parity check matrix.

More preferably, the ensuring step further comprises the step ofprearranging columns of the data portion H_(d) of the selected expandedparity check matrix.

Preferably, the method further comprises the steps of a) selectingN_(punctured) variable nodes from the selected expanded parity checkmatrix; b) ensuring each of the selected N_(punctured) variable nodes isconnected to fewest possible check nodes; and c) ensuring that all ofthe selected N_(punctured) nodes are connected to most possible checknodes.

Preferably, the performance criterion is selected from the groupconsisting of a threshold for N_(punctured), a threshold forN_(shortened), a threshold for normalized shortening to puncturingratio, q_(normalized), and a combination thereof; wherein q_(normalized)is defined as:q_(normalized)=(N_(shortened)/N_(punctured))/[R/(1−R)].

More preferably, the threshold for a q_(normalized) is set to be in therange of 1.2-1.5.

More preferably, the threshold for q_(normalized) is set to be equal to1.2.

In accordance with another aspect of the present invention there isprovided a method of shortening low-density parity-check (LDPC) codecomprising the steps of: a) selecting variable nodes in a parity checkmatrix; b) ensuring a uniform or a close to uniform row weightdistribution after removing the selected variable nodes; and c) ensuringa new column weight distribution as close as possible to an originalcolumn weight distribution after removing the columns corresponded tothe selected variable nodes.

Preferably, the method further comprises the step of selecting variablenodes that belongs to consecutive columns in the parity check matrix.

Preferably, the method further comprises the step of prearrangingcolumns of the data portion of parity check matrix.

In accordance with another aspect of the present invention there isprovided a method of puncturing a low-density parity-check (LDPC) codecomprising the steps of: a) selecting variable nodes in a parity checkmatrix; b) ensuring that each of the selected variable nodes isconnected to fewest possible check nodes; and c) ensuring that all ofthe selected variable nodes are connected to most possible check nodes.

Preferably, the method further comprises the step of selecting variablenodes belonging to consecutive columns in the parity check matrix.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and the illustrated embodiments may be better understood,and the numerous objects, advantages, and features of the presentinvention and illustrated embodiments will become apparent to thoseskilled in the art by reference to the accompanying drawings, andwherein:

FIG. 1 shows a typical system in which embodiments of the presentinvention may be practiced;

FIG. 2 is an example of a structured LDPC code parity check matrix;

FIG. 3 depicts an example of a parity check matrix with dual diagonal;

FIG. 4 illustrates an example of unstructured data portion in a baseparity check matrix;

FIG. 5 is an example of the expanded unstructured base parity checkmatrix of FIG. 4;

FIG. 6 is an example of a parity check matrix expansion;

FIG. 7 is another example showing a base parity check matrix and anexpanded parity check matrix;

FIG. 8 depicts a general form of the base parity check matrix of thepresent invention;

FIG. 9 gives examples of parity portion H_(p) of the general base paritycheck matrix allowing efficient encoding;

FIG. 10 is an example of a fully structured base parity check matrix,showing sub-matrices arranged as blocks;

FIG. 11 is an expanded parity check matrix from sub-matrices of thefully structured base parity check matrix of FIG. 10;

FIG. 12 illustrates the general form of the parity check matrix of thepresent invention;

FIG. 13 shows a parity check matrix with outlined layers for the layeredbelief propagation decoding;

FIG. 14 gives the high level hardware architecture implementing existingmethod of layered belief propagation decoding;

FIG. 15 is an example of the high level hardware architectureimplementing layered belief propagation decoding in accordance with oneembodiment of the present invention;

FIG. 16 shows a sub-matrix construction by concatenation of permutationmatrices;

FIG. 17 is an example of parallel decoding with concatenated permutationmatrixes;

FIG. 18 is an example of modifications supporting parallel decoding whensub-matrices are built from concatenated smaller permutation matrices;

FIG. 19 illustrates short and long information blocks processing;

FIG. 20 illustrates encoding of data packets, using puncturing andshortening;

FIG. 21 illustrates a data encoding procedure in accordance with anotherembodiment of the present invention;

FIG. 22 illustrates rearranging of the columns in H_(d) in order toenable efficient shortening;

FIG. 23 shows a bipartite graph of an LDPC code with emphasis on apunctured bit;

FIG. 24 illustrates puncturing impact on the performance;

FIG. 25 is an example of a parity check matrix suited for bothpuncturing and shortening operation and used to obtain the resultsillustrated in FIG. 24; and

FIGS. 26a, 26b and 26c are matrices for use in relevant encoding methodsand systems.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Reference will now be made in detail to some specific embodiments of theinvention including the best modes contemplated by the inventors forcarrying out the invention. Examples of these specific embodiments areillustrated in the accompanying drawings. While the invention isdescribed in conjunction with these specific embodiments, it will beunderstood that it is not intended to limit the invention to thedescribed embodiments. On the contrary, it is intended to coveralternatives, modifications, and equivalents as may be included withinthe spirit and scope of the invention as defined by the appended claims.In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Thepresent invention may be practiced without some or all of these specificdetails. In other instances, well-known process operations have not beendescribed in detail in order not to unnecessarily obscure the presentinvention.

Efficient decoder architectures are enabled by designing the paritycheck matrix, which in turn defines the LDPC code, around somestructural assumptions: structured LDPC codes.

One example of this design is that the parity check matrix comprisessub-matrices in the form of binary permutation or pseudo-permutationmatrices.

The term “permutation matrix” is intended to mean square matrices withthe property that each row and each column has one element equal to 1and other elements equal to 0. Identity matrix, a square matrix withones on the main diagonal and zeros elsewhere, is a specific example ofpermutation matrix. The term “pseudo-permutation matrix” is intended toinclude matrices that are not necessarily square matrices, and matricesmay have row(s) and/or column(s) consisting of all zeros. It has beenshown, that using this design, significant savings in wiring, memory,and power consumption are possible while still preserving the mainportion of the coding gain. This design enables various serial,parallel, and semi-parallel hardware architectures and therefore varioustrade-off mechanisms.

This structured code also allows the application of layered decoding,also referred to as layered belief propagation decoding, which exhibitsimproved convergence properties compared to a conventional sum-productalgorithm (SPA) and its derivations. Each iteration of the layereddecoding consists of a number of sub-iterations that equals the numberof blocks of rows (or layers). FIG. 2 shows a matrix having three suchlayers 21, 22, 23.

LDPC code parity check matrix design also results in the reduction inencoder complexity. Classical encoding of LDPC codes is more complexthan encoding of other advanced codes used in FEC, such as turbo codes.In order to ease this complexity it has become common to designsystematic LDPC codes with the parity portion of the parity check matrixcontaining a lower triangular matrix. This allows simple recursivedecoding. One simple example of a lower triangular matrix is a dualdiagonal matrix as shown in FIG. 3.

Referring to FIG. 3, the parity check matrix 30 is partitioned asH=[H_(d)|H_(p)]. Data portion H_(d) 31 is an M×K matrix that correspondsto the data bits of the codeword. The design of the H_(d) 31 matrixensures high coding gain. Parity portion H_(p) 32 is in this example anM×M dual diagonal matrix and corresponds to the parity bits of thecodeword. These codes are systematic block codes. The codeword vectorfor these systematic codes has the structure:

$c = \left\lbrack \frac{d}{p} \right\rbrack$where d=[d₀ . . . d_(k−1)]^(T) is the block of data bits and p=[p₀ . . .p_(M−1)]^(T) are the parity bits. A codeword is any binary, or ingeneral, non-binary, N-vector c that satisfies:Hc=H_(d)d+H_(p)p=0

Thus, a given data block d is encoded by solving binary equationH_(d)d=H_(p)p for the parity bits p. In principle, this involvesinverting the M×M matrix H_(p) to resolve p:p=H_(p) ⁻¹H_(d)d   [equation 1]

H_(p) is assumed to be invertible. If the inverse of H_(p), H_(p) ⁻¹ isalso low density then the direct encoding specified by the above formulacan be done efficiently. However, with the dual diagonal structure ofH_(p) 32 encoding can be performed as a simple recursive algorithm:

${p_{0} = {\overset{k_{0}}{\sum\limits_{n = 1}}{h_{0.i_{n}^{0}}d_{i_{n}^{0}}}}},$where i_(n) ⁰ is the index of the column in which row 0 contains a “1”

${p_{1} = {p_{0} + {\overset{k_{1}}{\sum\limits_{n = 1}}{h_{1.i_{n}^{1}}d_{i_{n}^{1}}}}}},$where i_(n) ¹ is the index of the column in which row 1 contains a “1”

$\ldots{{p_{M - 1} = {p_{M - 2} + {\sum\limits_{n = 1}^{k_{M - 1}}{h_{{M - 1},i_{n}^{M - 1}}d_{i_{n}^{M - 1}}}}}},}$where i_(n) ^(M−1) is the index of the column in which row M−1 containsa “1”.

In these recursive expressions h_(r,c) are non-zero elements (1 in thisexemplary matrix) of the data portion of the parity check matrix, H_(d)31. The number of non-zero elements in rows 0, 1, . . . , M−1, isrepresented by k₀, k₁, . . . , k_(M−1), respectively.

One desirable feature of LDPC codes is that they support variousrequired code rates and block sizes. A common approach is to have asmall base parity check matrix defined for each required code rate andto support various block sizes by expanding the base parity checkmatrix. Since it is usually required to support a range of block sizes,a common approach is to define expansion for the largest block size andthen apply other algorithms which specify expansion for smaller blocksizes. Below is an example of a base parity check matrix:

11  0 10  6  3  5 −1  0 −1 −1 −1 −1 10  9  2  2  3  0 −1  0  0 −1 −1 −1 7  9 11 10  4  7 −1 −1  0  0 −1 −1  9  2  4  6  5  3  0 −1 −1  0  0 −1 3 11  2  4  2 11 −1 −1 −1 −1  0  0  2  7  1  0 10  7  1 −1 −1 −1 −1  0

In this example the base parity check matrix is designed for the coderate R=½ and its dimensions are (M_(b)×N_(b))=(6×12). Assume that thecodeword sizes (lengths) to be supported are in the range N=[72, 144],with increments of 12, i.e. N=[72, 84, . . . , 132, 144]. In order toaccommodate those block lengths the parity check matrix needs to be ofthe appropriate size (i.e. the number of columns match N, the blocklength). The number of rows is defined by the code rate: M=(1−R) N. Theexpansion is defined by the base parity check matrix elements and theexpansion factor L, which results in the maximum block size. Theconventions used in this example, for interpreting the numbers in thebase parity check matrix, are as follows:

-   -   −1, represents L×L all-zero square matrix, 0_(L), L equals 12 in        this example;    -   0, represents L×L identity matrix, I_(L).    -   integer, r (<L), represents L×L identity matrix, I_(L), rotated        to the right (for example) a number of times corresponding to        the integer.

The following example shows a rotated identity matrix where the integerspecifying rotation is 5:

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 00 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 00 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Therefore, for the largest block (codeword) size of N=144, the baseparity check matrix needs to be expanded by an expansion factor of 12.That way the final expanded parity check matrix to be used for encodingand generating the codeword of size 144, is of the size (72×144). Inother words, the base parity check matrix was expanded L_(max)=12 times(from 6×12 to 72×144). For the block sizes smaller than the maximum, thebase parity check matrix is expanded by a factor L<L_(max). In this caseexpansion is performed in the similar fashion except that now matricesI_(L) and 0_(L), are used instead of I_(Lmax) and 0_(Lmax),respectively. Integers specifying the amount of rotation of theappropriate identity matrix, I_(L), are derived from those correspondingto the maximum expansion by applying some algorithm. For example, suchan algorithm may be a simple modulo operation:r_(L)=(r_(Lmax))modulo L

An example of such a matrix is shown in FIG. 4 where the data portionH_(d) 61 and the parity portion H_(p) 62 of a matrix 60. Thecorresponding expanded parity check matrix is shown in FIG. 5 alsohaving a data portion H_(d) 71 and the parity portion H_(p) 72 of thematrix 70. Each of the shaded squares 73 indicates a L×L smallpermutation matrix that is placed on the position of the 1's in the baseparity check matrix, where L is the expansion factor. In other words, ifthe size of the base parity check matrix was M_(b)×N_(b), the size ofexpanded parity check matrix is now M×N=LM_(b)×LN_(b).

The expansion may be done for example by replacing each non-zero elementwith a permutation matrix of the size of the expansion factor. Oneexample of performing expansion is as follows.

H_(p) is expanded by replacing each “0” element by an L×L zero matrix,0_(L×L), and each “1” element by an L×L identity matrix, I_(L×L), whereL represent the expansion factor.

H_(d) is expanded by replacing each “0” element by an L×L zero matrix,0_(L×L), and each “1” element by a circularly shifted version of an L×Lidentity matrix, I_(L×L). The shift order, s (number of circular shifts,for example, to the right) is determined for each non-zero element ofthe base parity check matrix.

It should be apparent to a person skilled in the art that theseexpansions can be implemented without the need to significantly changethe base hardware wiring.

FIG. 6 shows an example of a base parity check matrix 41 and acorresponding expanded parity check matrix 42 using 3×3 sub-matrices ofwhich that labeled 43 is an example.

The simple recursive algorithm described earlier can still be applied ina slightly modified form to the expanded parity check matrix. If h_(i,j)represent elements of the H_(d) portion of the expanded parity checkmatrix, then parity bits can be determined as follows:p₀=h_(0,0)d₀+h_(0,1)d₁+h_(0,2)d₂+ . . . +h_(0,11)d₁₁p₁=h_(1,0)d₀+h_(1,1)d₁+h_(1,2)d₂+ . . . +h_(1,11)d₁₁p₂=h_(2,0)d₀+h_(2,1)d₁+h_(2,2)d₂+ . . . +h_(2,11)d₁₁p₃=p₀+h_(3,0)d₀+h_(3,1)d₁+h_(3,2)d₂+ . . . +h_(3,11)d₁₁p₄=p₁+h_(4,0)d₀+h_(4,1)d₁+h_(4,2)d₂+ . . . +h_(4,11)d₁₁p₅=p₂+h_(5,0)d₀+h_(5,1)d₁+h_(5,2)d₂+ . . . +h_(5,11)d₁₁p₆=p₃+h_(6,0)d₀+h_(6,1)d₁+h_(6,2)d₂+ . . . +h_(6,11)d₁₁p₇=p₄+h_(7,0)d₀+h_(7,1)d₁+h_(7,2)d₂+ . . . +h_(7,11)d₁₁p₈=p₅+h_(8,0)d₀+h_(8,1)d₁+h_(8,2)d₂+ . . . +h_(8,11)d₁₁p₉=p₆+h_(9,0)d₀+h_(9,1)d₁+h_(9,2)d₂+ . . . +h_(9,11)d₁₁p₁₀=p₇+h_(10,0)d₀+h_(10,1)d₁+h_(10,2)d₂+ . . . +h_(10,11)d₁₁p₁₁=p₈+h_(11,0)d₀+h_(11,1)d₁+h_(11,2)d₂+ . . . +h_(11,11)d₁₁

However, when the expansion factor becomes large, then the number ofcolumns with only one non-zero element, i.e. 1 in the example here, inthe H_(p) becomes large as well. This may have a negative effect on theperformance of the code.

One remedy for this situation is to use a slightly modified dualdiagonal H_(p) matrix. This is illustrated with reference to FIG. 7where the modified base parity check matrix 51 produces the expandedparity check matrix 52.

The parity check equations now become:h_(0,0)d₀h_(0,1)d₁+ . . . +h_(0,11)d₁₁+p₀+p₃=0   [Equation 2]h_(1,0)d₀h_(1,1)d₁+ . . . +h_(1,11)d₁₁+p₁+p₄=0   [Equation 3]h_(2,0)d₀h_(2,1)d₁+ . . . +h_(2,11)d₁₁+p₂+p₅=0   [Equation 4]h_(3,0)d₀h_(3,1)d₁+ . . . +h_(3,1)d₁₁+p₀+p₃+p₆=0   [Equation 5]h_(4,0)d₀h_(4,1)d₁+ . . . +h_(4,11)d₁₁+p₁+p₄+p₇=0   [Equation 6]h_(5,0)d₀h_(5,1)d₁+ . . . +h_(5,11)d₁₁+p₂+p₅+p₈=0   [Equation 7]h_(6,0)d₀h_(6,1)d₁+ . . . +h_(6,11)d₁₁+p₆+p₉=0   [Equation 8]h_(7,0)d₀h_(7,1)d₁+ . . . +h_(7,11)d₁₁+p₇+p₁₀=0   [Equation 9]h_(8,0)d₀h_(8,1)d₁+ . . . +h_(8,11)d₁+p₈+p₁₁=0   [Equation 10]h_(9,0)d₀h_(9,1)d₁+ . . . +h_(9,11)d₁₁+p₀+p₉=0   [Equation 11]h_(10,0)d₀h_(10,1)d₁+ . . . +h_(10,11)d₁₁+p₁+p₁₀=0   [Equation 12]h_(11,0)d₀h_(11,1)d₁+ . . . +h_(11,11)d₁₁+p₂+p₁₁=0   [Equation 13]

Now by summing up equations 2, 5, 8, and 11, the following expression isobtained:(h_(0,0)+h_(3,0)+h_(6,0)+h_(9,0))d₀+(h_(0,1)+h_(3,1)+h_(6,1)+h_(9,0))d₁. . .+(h_(0,11)+h_(3,11)+h_(6,11)+h_(9,11))d₁₁p₀+p₃+p₀+p₃+p₆+p₆+p₉+p₀+p₉=0

Since only p₀ appears an odd number of times in the equation above, allother parity check bits cancel except for p₀, and thus:p₀=(h_(0,0)+h_(3,0)+h_(6,0)+h_(9,0))d₀+(h_(0,1)+h_(3,1)+h_(6,1)+h_(9,1))d₁+.. . +(h_(0,11)+h_(3,11)+h_(6,11)+h_(9,11))d₁₁

Likewise:p₁=(h_(1,0)+h_(4,0)+h_(7,0)+h_(10,0))d₀+(h_(1,1)+h_(4,1)+h_(7,1)+h_(10,1))d₀+(h_(1,11)+h_(4,11)+h_(7,11)+h_(10,11))d₁₁p₂=(h_(2,0)+h_(5,0)+h_(8,0)+h_(11,0))d₀+(h_(2,1)+h_(5,1)+h_(87,1)+h_(11,1))d₁+.. . +(h_(2,11)+h_(5,11)+h_(8,11)+h_(11,11))d₁₁

After determining p₀, p₁, p₂ the other parity check bits are obtainedrecursively:p₃=h_(0,0)d₀+h_(0,1)d₁+. . . +h_(0,11)d₁₁+p₀p₄=h_(1,0)d₀+h_(1,1)d₁+. . . +h_(1,11)d₁₁+p₁p₅=h_(2,0)d₀+h_(2,1)d₁+. . . +h_(2,11)d₁₁+p₂p₆=h_(3,0)d₀+h_(3,1)d₁+. . . +h_(3,11)d₁₁+p₀+p₃p₇=h_(4,0)d₀+h_(4,1)d₁+. . . +h_(4,11)d₁₁+p₁+p₄p₈=h_(5,0)d₀+h_(5,1)d₁+. . . +h_(5,11)d₁₁+p₂+p₅p₉=h_(6,0)d₀+h_(6,1)d₁+. . . +h_(6,11)d₁₁+p₆p₁₀=h_(7,0)d₀+h_(7,1)d₁+. . . +h_(7,11)d₁₁+p₇p₁₁=h_(8,0)d₀+h_(8,1)d₁+. . . +h_(8,11)d₁₁+p₈   [Equation 14]

The present invention provides method and system enabling highthroughput, low latency implementation of LDPC codes, and preserving thesimple encoding feature at the same time.

In accordance with one embodiment of the present invention, a generalform is shown in FIG. 8 where the matrix 80 has a data portion H_(d) 81and a parity portion H_(p) 82. Each of the shaded blocks 83 represents asub-matrix. A sub-matrix may be, for example, but not limited to, apermutation matrix, a pseudo-permutation matrix or a zero matrix. Whenefficient encoding is required, the parity portion H_(p) 82 of thematrix is designed such that its inverse is also a sparse matrix.Elements of the base parity check matrix and its sub-matrices may bebinary or non-binary (belonging to elements of a finite Galois Field ofq elements, GF(q)).

The data portion (H_(d)) may also be placed on the right side of theparity (H_(p)) portion of the parity check matrix. In the most generalcase, columns from H_(d) and H_(p) may be interchanged.

Parity check matrices constructed according to the embodiments of thepresent invention supports both regular and irregular types of theparity check matrix. Not only the whole matrix may be irregular(non-constant weight of its rows and columns) but also that itsconstituents H_(d) and H_(p) may be irregular, if such a partition isdesired.

If the base parity check matrix is designed with some additionalconstraints, then base parity check matrices for different code ratesmay also be derived from one original base parity check matrix in one oftwo ways:

-   -   a. Row combining: higher rate base parity check matrices are        derived from an original lower rate base parity check matrix by        combining rows of the base parity check matrix. Multiple        strategies can be applied in order to make the resultant higher        rate base matrix maintain the properties of the original matrix,        i.e. the weight of each of the column in a block of rows is at        most one. One way of doing row combining will be to combine (add        together) rows that belong to the same block of rows. This        guarantees the preservation of column weight properties, with        decrease of the block row size. Another way of row combining        will be to combine the rows that belong to different blocks of        rows, where they don't have overlapping elements.    -   b. Row splitting: lower rate base parity check matrices are        derived from an original higher rate base parity check matrix by        splitting rows of the base parity check matrix. The resultant        lower rate parity check matrix shall maintain the properties of        the original matrix, i.e. the weight of each of the column in a        block of rows is at most one.

Row-combining or row-splitting, with the specific constraints definedabove, allow efficient coding of a new set of expanded derived baseparity check matrices. In these cases the number of layers may be as lowas the minimum number of block rows (layers) in the original base paritycheck matrix.

FIG. 9 shows examples for parity portion H_(p)'s of these base paritycheck matrices allowing more efficient encoding. In each example, zerosub-matrices 91 are shown lightly shaded with a 0, and permutation (orpseudo-permutation) sub-matrices 90 are shown cross-hatched. In FIG. 9,parity portions with sub-matrices 901, 902 are examples of theembodiments of the invention. Parity portions with sub-matrices 903, 904represent particularly interesting cases of the generalized dualdiagonal form. The first column 95 of the sub-matrix of the parityportion 903, and the last column 96 of the parity portion 904 contain anodd number of sub-matrices in order to ensure the existence of theinverse matrix of H_(p). The other columns each contain two sub-matricesin pairs, forming a “staircase”, which ensures efficient recursiveencoding. These constructions of H_(p) can be viewed as generalizedcases, where H_(p) consists of a dual diagonal and an odd-weight column(such as the matrix 60 in FIG. 4), which may be symbolically expressedas:H_(p,present_invention)(m)=T (H_(p,existing),m),

Where T is the transform describing the base parity check matrixexpansion process and m is the size of the permutation matrices. Form=1, H_(p) of the present invention defines the form of the prior artH_(p) (dual diagonal with the odd-weight column), i.e.

H_(p,present_invention)(l)=T (H_(p,existing),l)=H_(p,existing)

A further pair of parity portions with sub-matrices 905, 906 illustratecases where these first and last columns, respectively, have only onesub-matrix each.

The two parity portions with sub-matrices 907, 908 in FIG. 9 illustratelower and upper triangular structure, also thus permit efficientrecursive encoding. However, in order to solve the weight-1 problem, thesub-matrices 99 (shown hatched) in each example have the weight of allcolumns equal to 2, except the last one, which has weight equal to 1.

One of the characteristics of the base parity check matrix expansion ofthe present invention is that the expanded base parity check matrixinherits structural features from the base parity check matrix. In otherwords, the number of blocks (rows or columns) that can be processed inparallel (or serial, or in combination) in the expanded parity checkmatrix equals the number of blocks in the base parity check matrix.

Referring to FIG. 10, matrix 100 representing one possible realizationof a rate R=½ base parity check matrix based on the structure of thematrix 80 of FIG. 8. In the matrix 100, only non-zero elements (1's inthis example) are indicated and all blanks represent 0's. The paritycheck matrix comprises D rows that may be processed in parallel (D=4 formatrix 100). Each row can be further split into a number of columns, B(B=8 for matrix 100). Therefore, the whole base parity check matrix 100can be envisioned as comprising D rows and B columns of sub-matrices.Examples of the sub-matrices may be, but not limited to, permutationsub-matrices, pseudo-permutation sub-matrices or zero sub-matrices.Furthermore, it is not necessary that the sub-matrices are squaresub-matrices, although in this example all sub-matrices are m×m squaresub-matrices.

The base parity check matrix 100 of FIG. 10 is shown as an expandedparity check matrix 110 in FIG. 11. In this example, each non-zeroelement is replaced by a L×L sub-matrix, for example a permutationsub-matrix, and each zero is replaced by an L×L zero sub-matrix of whichthe smaller square 111 is an example.

It can be seen that expanded parity check matrix 110 has inheritedstructural properties of its base parity check matrix 100 from FIG. 10.That means that in the expanded sub-matrix blocks (of which 112 is anexample) can be considered as having the same sub-matrices as before theexpansion, for example, permutation, or all zero sub-matrices. Thisproperty offers implementation advantages.

The sub-matrices of the present invention are not limited to permutationsub-matrices, pseudo-permutation sub-matrices or zero sub-matrices. Inother words, the embodiments of the present invention are not restrictedto the degree distribution (distribution of column weights) of theparity check matrix, allowing the matrix to be expanded to accommodatevarious information packet sizes and can be designed for various coderates. This generalization is illustrated through following examples.

FIG. 12 shows a general form of a parity check matrix 120. Cross-hatchedblocks, of which 121 is an example, represent sub-matrices S, which maybe, in the most general form, rectangular. In addition, thesesub-matrices 121 may further comprise a set of smaller sub-matrices ofdifferent size. As discussed before, elements of the parity check matrixand its sub-matrices may be binary or non-binary (belonging to elementsof a finite Galois Field of q elements, GF(q)).

FIG. 13 shows a parity check matrix 130 having rows corresponding todifferent layers l to D, of which 132, 133, 134 are examples.

In the context of parallel row processing, layered belief propagationdecoding is next briefly described with reference to FIGS. 13 and 14.

A high level architectural block diagram is shown in FIG. 14 for theparallel row processing scenario comprising memory modules 141,connected to a read network 142 (using permuters). These permuters arein turn connected to a number of processing units 143 whose outputs aredirected to a write network 144 (using inverse permuters). In thisscenario, each iteration of the belief propagation decoding algorithmconsists of processing D layers (groups of rows). This approachtherefore updates the decoding variables corresponding to a particularlayer depends on the equivalent variables corresponding to all otherlayers.

In order to support a more general approach in accordance with anembodiment of the present invention, the architecture of FIG. 14 may bemodified. One example of such a modification is depicted in FIG. 15where the extra inter-layer storage element 155 is shown. In this newarchitecture additional storage of inter-layer variables is alsorequired—the function being provided by the element 155. This changeenables an increased level of parallelism beyond the limits of existingapproach.

By exercising careful design of the parity check matrix, the additionalinter-layer storage 155 in FIG. 15 can be implemented with lowcomplexity. One such approach is discussed below.

Iterative parallel decoding process is best described asread-modify-write operation. The read operation is performed by a set ofpermuters, which deliver information from memory modules tocorresponding processing units. Parity check matrices, designed with thestructured regularity described earlier, allow efficient hardwareimplementations (e.g., fixed routing, use of simple barrel shifters) forboth read and write networks. Memory modules are organized so as toprovide extrinsic information efficiently to processing units.

Processing units implement block (layered) decoding (updating iterativeinformation for a block of rows) by using any known iterative algorithms(e.g. Sum Product, Min-Sum, Bahl-Cocke-Jelinek-Raviv (BCJR)).

Inverse permuters are part of the write network that performs the writeoperation back to memory modules.

Such parallel decoding is directly applicable when the parity checkmatrix is constructed based on permutation, pseudo-permutation or zerosub-matrices.

To encode using sub-matrices other than permutation, pseudo-permutationor zero sub-matrices, one embodiment of the present invention usesspecial sub-matrices. A sub-matrix can also be constructed byconcatenation of smaller permutation or pseudo-permutation matrices. Anexample of this concatenation is illustrated in FIG. 16, in which thefour small sub-matrices 161, 162, 163, 164 are concatenated into thesub-matrix 165.

Parallel decoding is applicable with the previously describedmodification to the methodology; that is, when the parity check matrixincludes sub-matrices built by concatenation of smaller permutationmatrices.

FIG. 17 illustrates such a base matrix 170. The decoding layer 171includes permutation sub-matrices 172 S₂₁, S₂₂, S₂₃, S₂₆, S₂₇,sub-matrix S₂₄ (built by concatenation of smaller permutation matrices),and zero sub-matrices S₂₅, and S₂₈. The decoding layer 171 is shown 174with the sub-matrix S₂₄ split vertically into S¹ ₂₄ 176 and S² ₂₄ 177.

It can be seen that for the decoding layer 171 a first processing unitreceives information in the first row 179 from bit 1 (according to S₂₁),bit 6 (S₂₂), bit 9 (S₂₃), bit 13 (S¹ ₂₄), bit 15 (S² ₂₄), bit 21 (S₂₈),and bit 24 (S₂₉). Other processing units are loaded in a similar way.

For layered belief propagation type decoding algorithms, the processingunit inputs extrinsic information accumulated, by all other layers,excluding the layer currently being processed. Thus, the prior artimplementation described using FIG. 14 presents the processing unit withall the results accumulated by other decoding layers. The only bits thatrequire modification in order to satisfy this requirement are bits fromS¹ ₂₄ 176 and S² ₂₄ 177, which are referred to as special bits. Toprovide complete extrinsic information about these special bits to aprocessing unit, an output must be added from other variable nodeswithin the current layer (inter-layer results) as described previouslywith respect to FIG. 15 where the interlayer storage element 155 wasintroduced.

This is illustrated in FIG. 18 in which additional memory modules 155used for interlayer storage are shown, and which provide interlayerextrinsic information to permuters 1821, 1822, 1829. For the specialbits the additional storage for inter-layer information comprises thedelay lines 186. Processing units 184a-184d, each programmed tocorrespond with a row 179 of the current decoding layer 174, provideinputs to delay lines 186. A first further permuter 1851 is applied tochoose a pair of processing units 184 that operate with same specialbit. A second further permuter 1852 chooses a processing unit's“neighbor”—namely one that operates with same special bit at the currentdecoding layer. Adders 1831a-1831d combine intra-layer information withinter-layer results from the second further permuter 1852. Outputs fromthe first further permuter 1851 are combined using adders 1835a and1835b whose outputs enter the inverse permuters 187 as well as all other“normal” (i.e. non-special bits) bits output from each processing unit184. The outputs from the inverse permuters 187 are written back to thememory modules 155 (intra-layer storage). Processing continues for thecomplete code matrix 170, taking each layer 174 in turn.

For simplicity, FIG. 18 shows details of modifications for special bitscoming from S¹ ₂₄ 176. The analogous modifications for S² ₂₄ 177 arealso included in embodiments of the invention.

Improvement in throughput, and reduction in latency in accordance to anembodiment of the present invention is further illustrated by thefollowing example.

The LDPC codes can be decoded using several methods. In general,iterative decoding is applied. The most common is the sum-productalgorithm (SPA) method. Each iteration in SPA comprises two steps:

-   -   a. horizontal step, during which all row variables are updated        at the same time based on the column variables; and    -   b. vertical step, during which all column variables are updated        at the same time based on row variables.

It has been shown that better performance, in terms of the speed ofconvergence, can be achieved with layered decoding. In layered decodingonly row variables are updated for a block of rows, one block row at atime. The fastest approach is to process all the rows within a block ofrows simultaneously.

The following is a comparison of the achievable throughput (bit rate) oftwo LDPC codes: one based on the existing method for expanding matrix,as described in FIG. 5, and the other based on the matrix of the presentinvention as described in FIG. 17. Throughput in bits per second (bps)is defined as:T=(K×F)/(C×I),where K is number of info bits, F is clock frequency, C is number ofcycles per iteration, and I is the number of iterations. Assuming thatK, F, and I are fixed and, for example, equal: K=320 bits, F=100 MHz,and I=10, the only difference between the existing method and thepresent invention is derived from C, the factor which is basically ameasure of the level of allowed parallelism. It can be seen, bycomparing FIG. 5 and FIG. 17, that the number of rows is the same inboth cases (M_(b)=16). Assuming that the expanded parity check matricesare also the same size, and the same payload of, for example, K=320 bitscan also be handled, an expansion factor of 20 (L=320/16) will berequired. The maximum number of rows that can be handled in parallel isL (=20) for the matrix of FIG. 5, whereas the number of rows forparallel operation in the case of FIG. 17 is 4×20=80. Thus the number ofcycles per iteration, C, is given as follows:C_(existing)=16 and C_(present_invention)=4.

Using these numbers in the formula gives:T_(max,existing)=200 MbpsT_(max,present_invention)=800 Mbps

As expected, the maximum throughput is 4 times greater. All thedesirable features of the code design in terms of efficient encoding arepreserved. For example, without degradation in performance, the encodingalgorithm as described earlier with respect to FIG. 2, and thecorresponding efficient encoder architecture still apply.

Furthermore, when a scaleable solution is desired, the size of theexpanded LDPC parity check matrix is designed to support the maximumblock size. The existing solutions do not scale well with respect to thethroughput for various block sizes. For example, using the existingmethod for layered decoding, processing of short and long blocks takesthe same amount of time. This is caused by the fact that for shorterblocks, not all processing units are used, resulting proportionallylower achieved throughput.

The following example is based on the same example as before bycomparing matrices as described earlier in FIG. 5 and FIG. 17. Oneembodiment of the present invention allows the splitting of a block ofrows into smaller stripes, and still has a reasonably low number ofcycles per layered decoding iteration. The existing architecture doesnot allow this splitting without increasing decoding time beyond areasonable point.

FIG. 19 illustrates the difference between the prior art method and themethod in accordance with one embodiment of the present invention. Theblocks 191 and 192 represent short blocks as processed by one embodimentof the present invention and in the existing method, respectively. Inthe case using the embodiment of the present invention only 4 cycles arerequired per iteration, whereas prior art implementations require 16cycles. This represents a considerable savings in processing. Forcomparison, blocks 193 and 194 represent long blocks as processed by thepresent invention and in the prior art respectively, where as expectedthe savings are not made.

The following table compares the computed results.

Number of Codeword processing Throughput size C units (Mbps) Existing(FIG. 5)  320 16 20 200 1280 16 80 800 Embodiment of  320  4 80 800present invention (FIG. 17) 1280 16 80 800

It can be seen from the table that the embodiment of the presentinvention provides constant throughput independent on the codeword size,whereas in the case of the existing method the throughput for thesmaller blocks drops considerably. The reason is that while theembodiment of the present invention fully utilizes all availableprocessing resources irrespective of block size, the existing methodutilizes all processing units only in the case of the largest block, anda fraction of the total resources for other cases.

The example here illustrating the throughput improvement for shorterblocks, leads also to the conclusion that reduced latency is alsoachieved with the embodiment of the present invention. When large blocksof data are broken into smaller pieces, the encoded data is split amongmultiple codewords. If one places a shorter codeword at the end ofseries of longer codewords, then the total latency depends primarily onthe decoding time of the last codeword. According to the table above,short blocks require proportionally less time to be decoded (as comparedto the longer codewords), thereby allowing reduced latency to beachieved by encoding the data in suitably short blocks.

In addition to the full hardware utilization illustrated above,embodiments of the present invention allow hardware scaling, so thatshort blocks can use proportionately less hardware resources if anapplication requires it.

Furthermore, utilization of more efficient processing units and memoryblocks is enabled. Memory can be organized to process a number ofvariables in parallel. The memory can therefore, be partitioned inparallel.

The present invention provides new LPDC base parity matrices, andexpanded matrices based on the new base parity matrices, and method foruse thereof.

The locations of non-zero matrices for rate R in an exemplary matrix arechosen, so that:

-   -   a) parity part ((1−R)*24 rightmost columns) of the matrix is        designed to allow simple encoding algorithms;    -   b) weights of all columns in the data portion of base parity        check matrix is uniform;    -   c) weights of all rows in the data portion of a base parity        check matrix is uniform;    -   d) the parity part of the matrix allows simple encoding        algorithms. For example, the encoding algorithm based on        equation 1, or equation 14.

An example of R=¾ base parity check matrix design using criteria a) tod) is:

1 1 1 1 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 1 0 0 10 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 1 0 1 1 1 1 0 0 1 1 0 01 1 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 0 0 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 0 0 0 0 1

The rate R=¾ matrix definition built based on such base parity checkmatrix covers expansion factors in the range L between 24 and L_(max)=96in increments of 4. Right circular shifts of the corresponding L×Lidentity matrix s′_(ij), are determined as follows:

$s_{ij}^{\prime} = \left\{ \begin{matrix}{{{floor}\left( \frac{L \times s_{ij}}{L_{\max}} \right)},} & {s_{ij} > 0} \\{s_{ij},} & {{otherwise},}\end{matrix} \right.$where s_(ij) is specified in the matrix definition below:

 6 38  3 93 −1 −1 −1 30 70 −1 86 −1 37 38  4 11 −1 46 48  0 −1 −1 −1 −162 94 19 84 −1 92 78 −1 15 −1 −1 92 −1 45 24 32 30 −1 −1  0  0 −1 −1 −171 −1 55 −1 12 66 45 79 −1 78 −1 −1 10 −1 22 55 70 82 −1 −1  0  0 −1 −138 61 −1 66  9 73 47 64 −1 39 61 43 −1 −1 −1 −1 95 32  0 −1 −1  0  0 −1−1 −1 −1 −1 32 52 55 80 95 22  6 51 24 90 44 20 −1 −1 −1 −1 −1 −1  0  0−1 63 31 88 20 −1 −1 −1  6 40 56 16 71 53 −1 −1 27 26 48 −1 −1 −1 −1  0

The present invention further enables flexible rate adjustments by theuse of shortening, or puncturing, or a combination thereof. Block lengthflexibility is also enabled through expansion, shortening, orpuncturing, or combinations thereof.

Any of these operations can be applied to the base or expanded paritycheck matrices.

Referring to FIG. 20, a data packet of length L is required to beencoded using an LDPC code (N, K), as previously presented, K 202 is theinformation block size, N is the length of the codeword, and M 203 isthe number of parity check bits, M=N−K. The encoded data is to betransmitted using a number of modulated symbols, each carrying S bits.

The data packet 201 of length L is divided into segments 208. Thesesegments are in turn encoded using an LDPC code (N, K). The informationblock K 202 may be optionally pruned to K′ 204; and the parity checkbits M may be pruned to M′ 205. The term “pruning” is intended to meanapplying code shortening by sending less information bits than possiblewith a given code, (K′<K). The term “puncturing” is intended to meanremoving some of the parity bits and/or data bits prior to sending theencoded bits to the modulator block and subsequently over the channel.Pruned codewords may be concatenated 206 in order to accommodate theencoded data packet, and the resulting stream 207 is padded with bits209 to match the boundaries 210 of modulated symbols before being sentto the modulator. The amount of shortening and puncturing may bedifferent for the constituent pruned codewords. The objectives here are:

-   -   (a) Keep the performance in terms of coding gain as high as        possible. This objective translates into the following needs:        -   Select the largest suitable codeword from the available set            of codewords. For the LDPC codes and other block codes, the            longer the codeword the more coding gain can be achieved,            although at certain codeword size the point of diminishing            return is reached.        -   Adjust properly the amount of shortening and puncturing, as            this directly affects the performance, and the efficiency of            the transmission.    -   (b) Use as few of the modulated symbols as possible. This in        turn means that it is desirable to utilize transmit power        economically. This is especially important for battery operated        hand-held wireless devices by keeping the air time at minimum.    -   (c) Keep the overall complexity at a reasonable level. This        usually translates into a requirement to operate with a        relatively small set of codewords in different sizes. In        addition, it is desirable to have a code designed in such a way        that various codeword lengths can be implemented efficiently.        Finally, the actual procedure defining concatenation rules        should be simple.

From objective (a) above it follows that in order to use a small numberof codewords, an efficient shortening and puncturing operation needs tobe applied. However, those operations have to be implemented in a waythat would neither compromise the coding gain advantage of LDPC codes,nor lower the overall transmit efficiency unnecessarily. This isparticularly important when using the special class of LDPC parity checkmatrices that enable simple encoding operation, for example, as the onedescribe in the previous embodiments of the present invention. Thesespecial matrices employ either a lower triangular, a dual-diagonal, or amodified dual-diagonal in the parity portion of the parity check matrixcorresponding. An example of a dual-diagonal matrix is described earlierin FIG. 3 in which the parity portion H_(p) 32 corresponds to the paritybits, and the data portion H_(d) 31 to the information data bits.

Work to achieve efficient puncturing has been done using the “ratecompatible” approach. One or more LDPC parity check matrix is designedfor the low code rate application. By applying the appropriatepuncturing of the parity portion, the same matrix can be used for arange of code rates which are higher than the original code rate as thedata portion in relation to the codeword increases. These methodspredominantly target applications where adaptive coding (e.g. hybridautomatic repeat request, H-ARQ) and/or unequal bit protection isdesired.

Puncturing may also be combined with code extension to mitigate theproblems associated with “puncturing only” cases. The main problem thatresearchers are trying to solve here is to preserve an optimum degreedistribution through the process of modifying the original parity checkmatrix.

However, these methods do not directly address the problem describedearlier: apply shortening and puncturing in such a way that the coderate is approximately the same as the original one, and the coding gainis preserved.

One method attempting to solve this problem specifies shortening andpuncturing such that the code rate of the original code is preserved.The following notation is used:

N_(punctured)—Number of punctured bits,

N_(shortened)—Number of shortened bits.

Shortening to puncturing ratio, q, is defined as:q=N_(shortened)/N_(punctured).

In order to preserve the same code rate, q has to satisfy the followingequation:q_(rate_preserved)=R/(1−R)

Two approaches are prescribed for choosing which bits to shorten andwhich to puncture to reach a shortening and a puncturing pattern.

Two approaches for shortening and puncturing of the expanded matricesare described in Dale Hocevar and Anuj Batra, “Shortening and PuncturingScheme to Simplify LDPC Decoder Implementation,” Jan. 11, 2005, acontribution to the informal IEEE 802.16e LDPC ad-hoc group, theentirely of the document is incorporated herein by reference. Thesematrices are generated from a set of base parity check matrices, onebase parity check matrix per code rate. The choice depends on the coderate, i.e. on the particular parity check matrix design.

The method may preserve the column weight distribution, but may severelydisturb the row weight distribution of the original matrix. This, inturn, causes degradation when common iterative decoding algorithms areused. This adverse effect strongly depends on the structure of theexpanded matrix.

This suggests that this approach fails to prescribe general rules forperforming shortening and puncturing, and has an unnecessary restrictionfor a general case such as the one described in FIG. 20. Namely,accepting some reduction in the code rate in order to keep theperformance in terms of the coding gain at a certain level.

In general, the amount of puncturing needs to be limited. Extensivepuncturing beyond certain limits paralyzes the soft decision decoder.Prior art methods, none of which specify a puncturing limit oralternatively offer some other way for mitigating the problem, maypotentially compromise the performance significantly.

In accordance with another embodiment of the present invention, abovedescribed shortcomings may be addressed by:

-   -   (a) specifying general rules for shortening and puncturing        patterns;    -   (b) providing mechanism for q >q_(rate_preserved);    -   (c) establishing a limit on the amount of puncturing; and    -   (d) providing an algorithmic method for finding the optimal        solution within the range of given system parameters.

This embodiment of the present invention may be beneficially applied toboth the transmitter and the receiver. Although developed for wirelesssystems, embodiments of the invention can be applied to any othercommunication system which involves encoding of variable size datapackets by a fixed error correcting block code.

The advantage of this invention can be summarized as providing anoptimal solution to the above described problem given the range of thesystem parameters such as the performance, power consumption, andcomplexity. It comprises the following steps:

-   -   1. Based on the data packet size determine the minimum number of        required modulated symbols;    -   2. Select the codeword length from the set of available codeword        lengths;    -   3. In an iterative loop determine required amount of shortening        and puncturing and corresponding estimated performance and add        additional modulated symbol(s), if necessary;    -   4. Distribute amount of shortening and puncturing across all        constituent codewords efficiently; and    -   5. Append padding bits in the last modulated symbol if        necessary.        Referring to FIG. 21, these steps are more fully shown in the        flow chart in which the process starts 211 and various        parameters are input 212 including:    -   Data packet size in bits, L;    -   Set of codewords of size Ni (i=1, 2, . . . ,        number_of_codewords) for the derived code rate R;    -   Number of bits carried by a modulated symbol S; and    -   Performance criteria.

At step 213, the minimum number of modulated symbols N_(sym_min) iscalculated. Next at step 214, the codeword size N is selected, and thenumber of codewords to be concatenated N_(cwords) is computed. At step216 the required shortening and puncturing are computed, and performanceestimated. If the performance criterion are met 217, the number of bitsrequired to pad the last modulated symbol is computed 218 and theprocess ends 219. Where the performance criterion are not met 217, anextra modulated symbol is added 215 and the step 214 is reentered.

Both the encoder and the decoder may be presented with the same inputparameters in order to be able to apply the same procedure andconsequently use the same codeword size, as well as other relevantderived parameters, such as the amount of shortening and puncturing foreach of the codewords, number of codewords, etc.

In some cases only the transmitter (encoder) has all the parametersavailable, and the receiver (decoder) is presented with some derivedversion of the encoding procedure parameters. For example, in someapplications it is desirable to reduce the initial negotiation timebetween the transmitter and the receiver. In such cases the transmitterinitially informs the receiver of the number of modulated symbols it isgoing to use for transmitting the encoded bits rather than the actualdata packet size. The transmitter performs the encoding proceduredifferently taking into consideration the receiver's abilities (e.g.using some form of higher layer protocol for negotiation). Some of therequirements are relaxed in order to counteract deficiencies of theinformation at the receiver side. For example, the use of additionalmodulated symbols to enhance performance may always be in place, may bebypassed altogether, or may be assumed for the certain ranges of payloadsizes, e.g. indirectly specified by the number of modulated symbols.

One example of such an encoding procedure is an OFDM based transceiver,which may be used in IEEE 802.11n. In this case the reference to thenumber of bits per modulated symbol translates into the number of bitsper OFDM symbol. In this example, the AggregationFlag parameterspecified in 801.11n is used to differentiate between the case when boththe encoder and the decoder are aware of actual data packet size(AggregationFlag=0) and the case when the packet size is indirectlyspecified by the number of required OFDM symbols (AggregationFlag=1).

An exemplary algorithm in accordance with one embodiment of the presentinvention is with following parameters are now described:

Algorithm Parameters

-   -   NN_(max)=2304, NN_(min)=576, NN_(inc)=576: maximum, minimum and        increment of codeword lengths, effectively resulting 4 codeword        lengths: 576, 1152, 1728, 2304;    -   p_(max): maximum puncturing percentage, which is defined as:        -   number of punctured bits/total number of parity bits (%).

Algorithm Input

-   -   R: target code rate;    -   N_(CBPS): number of data bits in OFDM symbol;    -   AggregationFlag: Boolean signaling whether PSDU is an aggregate        of MPDUs (AggregationFlag=1),    -   HT_LENGTH: number of payload octets (AggregationFlag=0), or        number of OFDM symbols (AggregationFlag=1)

Algorithm Output:

-   -   NN: code length to use;    -   N_(CodeWords): number of codewords to use;    -   KK_(S),KK_(S_Last): number of information bits to send in first        codeword(s), and in last codeword;    -   N_(p), N_(p_Last): number of bits to puncture in first codeword        (s), and in last codeword;    -   N_(OFDM): number of OFDM symbols used;    -   N_(PaddingBits): number of bits the last OFDM symbol is padded;

Algorithm Procedure

if(AggregationFlag == 0) {  N_(InfoBits)=8×HT_LENGTH;  // innon-aggregation case HT_LENGTH is the number of payload  octetsN_(OFDM)=ceil(N_(InfoBits)/(N_(CBPS) × R));  // minimum number of OFDMsymbols }  else {  N_(OFDM) = HT_LENGTH;  // in aggregation caseHT_LENGTH is the number of OFDM symbols  N_(InfoBits) = N_(OFDM) ×N_(CBPS) × R;  // number of info bits includes padding;MAC will use itsown  delineation  //method to recover an aggregate payload } N_(CodeWords) = ceil(N_(CBPS)× N_(OFDM)/ NN_(max));  // number ofcodewords is based on maximum codeword length  NN = ceil(N_(CBPS)×N_(OFDM)/(N_(CodeWords)×NN_(inc)))× N_(inc);  // codeword length will bethe larger of the closest one  //to N_(CBPS) × N_(OFDM)/N_(CodeWords) KK=NN×R;  // number of information bits in codeword chosen MM=NN−KK; // number of parity bits in codeword chosen N_(ParityBits)_requested=N_(CodeWords)× MM;  // total number of parity bits allocated inN_(OFDM) symbols N_(ParityBits) =min(N_(OFDM)× N_(CRPS)−N_(InfoBits),N_(ParityBits)_requested);  // in non-aggregation caseallow adding extra OFDM symbol(s) to limit   //puncturingif(AggregationFlag==0) {   while(100× (N_(ParityBits)_requested−N_(ParityBits))/   N_(ParityBits)_requested >P_(max)) {    N_(OFDM) =N_(OFDM)+1;   // extra OFDM symbol(s) are used to carry parity  N_(ParityBits) = min(N_(ParityBits) +N_(CBPS),N_(ParityBits)_requested);   } }   // Finding number ofinformation bits to be sent per codeword(s),   //KK_(S), KK_(S)_Lasr andnumber of bits the codeword(s) will be punctured   N_(P) ,   //andN_(P)_Last, Making sure that last codeword may only be shortened   //more then others, and punctured less then others. KK_(S)=ceil(N_(InfoBits)/ N_(CodeWords)); KK_(S)_Last = N_(InfoBits) ~ KK_(S)× ( N_(CodeWords) −1); MM_(P) =min(MM,floor(N_(ParityBits)/_(CodeWords)); MM_(P)_Last = min(MM, N_(ParityBits)− MM_(P) × (N_(CodeWords) − 1)); N_(P) =MM − MM_(P); N_(P)_Last =MM−MM_(P)_Last;   // Finally, calculating number of padding bits in lastOFDM symbol N_(PaddingBits) = N_(OFDM) × N_(CBPS) − N_(InfoBits)−N_(ParityBits);

Each of those features will be now described in more detail.

(a) General Rules for Shortening and Puncturing

Much effort has been spent to come up with designs of LDPC parity checkmatrices such that the derived codes provide optimum performance.Examples include: T. J. Richardson et al., “Design ofCapacity-Approaching Irregular Length Low-Density Parity-Check Codes,”IEEE Transactions on Information Theory, vol. 47, February 2001 and S.Y. Chung, et al., “Analysis of Sum-Product Decoding of Low-DensityParity-Check Codes Using a Gaussian Approximation,” IEEE Transactions onInformation Theory, vol. 47, February 2001, both of which areincorporated herein by reference, are examples. These papers show that,in order to provide optimum performance, a particular variable nodesdegree distribution should be applied. Degree distribution refers hereto the distribution of the column weights in a parity check matrix. Thisdistribution, in general, depends on the code rate and the size of theparity check matrix, or codeword. It is desirable that the puncturingand shortening pattern, as well as the number of punctured/shortenedbits, are specified in such a way that the variable nodes degreedistribution is preserved as much as possible. However, since shorteningand puncturing are qualitatively different operations, different rulesapply to them, as will now be explained.

(b) Rules for Shortening

Shortening of a code is defined as sending less information bits thanpossible with a given code, K′<K. The encoding is performed by: takingK′ bits from the information source, presetting the rest (K-K′) of theinformation bit positions in the codeword to a predefined value, usually0, computing M parity bits by using the full M×N parity check matrix,and finally forming the codeword to be transmitted by concatenating K′information bits and M parity bits. One way to determine which bits toshorten in the data portion of the parity check matrix, H_(d) (31 inFIG. 3), is to define a pattern which labels bits to be shortened, giventhe parity check matrix, H=[H_(d)|H_(p)]. This is equivalent to removingcorresponding columns from H_(d). The pattern is designed such that thedegree distribution of the parity check matrix after shortening, i.e.removing appropriate columns from H_(d), is as close as possible to theoptimal one for the new code rate and the codeword length. To illustratethis, consider a matrix having the following sequence of weights (eachnumber corresponds to a column weight):

3 3 3 8 3 3 3 8 3 3 3 8

When discarding columns, the aim is to ensure that the ration of ‘3’s to‘8’s remains close to optimal, say 1:3 in this case. Obviously it cannotbe 1:3 when one to three columns are removed. In such circumstances, theremoval of 2 columns might result in e.g.:

3 3 8 3 3 8 3 3 3 8

giving a ratio of ˜1:3.3 and the removal of a third column—one withweight ‘8’—might result in:

3 3 3 3 8 3 3 3 8

thus preserving a ratio of 1:3.5, which is closer to 1:3 than would bethe case where the removal of the third column with weight ‘3’, whichresults in:

8 3 3 3 8 3 3 3 8

giving a ratio of 1:2.

It is also important to preserve approximately constant row weightthroughout the shortening process.

An alternative to the above-described approach is to prearrange columnsof the part of the parity check matrix, such that the shortening can beapplied to consecutive columns in H_(d). Although perhaps suboptimal,this method keeps the degree distribution of H_(d) close to the optimum.However, the simplicity of the shortening pattern, namely taking out theconsecutive columns of H_(d), gives a significant advantage by reducingcomplexity. Furthermore, assuming the original matrix satisfies thiscondition, approximately constant row weight is guaranteed. An exampleof this concept is illustrated in FIG. 22 where the original code rateR=½ matrix 220 is shown. In FIG. 22 (and FIG. 25) the white squaresrepresent a z x z zero matrix, whereas the gray squares represent a z×zidentity matrix shifted circularly to the right a number of timesspecified by the number written in the middle of the corresponding graysquare. In this particular case, the maximum expansion factor is:z_(max)=72.

After rearranging the columns of the H_(d) part of the original matrix,the new matrix takes on the form 221 shown in FIG. 22. It can be seenthat if the shortening is performed as indicated (to the left from theH_(d)|H_(p) boundary) the density of the new H_(d) will slightlyincrease until it reaches a “heavy” weight column (such as the blockcolumn 222). At that point the density of the new H_(d) will againapproach the optimum one. A person skilled in the art will note that therearranging of the columns in H_(d) does not alter the properties of thecode.

In the case of a regular column parity check matrix, or more generally,approximately regular, or regular and approximately regular only in thedata part of the matrix, H_(d), the method described in the previousparagraph is still preferred compared to the existing random orperiodic/random approach. The method described here ensuresapproximately constant row weight, which is another advantage from theperformance and the implementation complexity standpoint.

(c) Puncturing

Puncturing of a code is defined as removing parity bits from thecodeword. In a wider sense, puncturing may be defined as removing someof the bits, either parity bits or data bits or both, from the codewordprior to sending the encoded bits to the modulator block andsubsequently over the channel. The operation of puncturing, increasesthe effective code rate. Puncturing is equivalent to a total erasure ofthe bits by the channel. The soft iterative decoder assumes a completelyneutral value corresponding to those erased bits. In case that the softinformation used by the decoder is the log-likelihood ratio, thisneutral value is zero.

Puncturing of LDPC codes can be given an additional, somewhat different,interpretation. An LDPC code can be presented in the form of thebipartite graph of FIG. 23, in which the codeword bits are presented bythe variable nodes 231, and parity check equations by the check nodes232.

Each variable node 231 is connected 234 by edges, for example 233, toall the check nodes 232 in which that particular bit participates.Similarly, each check node (corresponding to a parity check equation) isconnected by a set of edges 237 to all variable nodes corresponding tobits participating in that particular parity check equation. If a bit ispunctured, for example node 235, then all the check nodes connected toit, those connected by thicker lines 236, are negatively affected.Therefore, if a bit chosen for puncturing participates in many paritycheck equations, the performance degradation may be very high. On theother hand, since the only way that the missing information(corresponding to the punctured bits) can be recovered is from themessages coming from check nodes those punctured bits participate in,the more of those the more successful recovery may be. Faced withcontradictory requirements, the optimum solution can be found somewherein the middle. These general rules can be stated as following:

-   -   Bits selected for puncturing should be chosen such that each one        is connected to as few check nodes as possible. This can be        equivalently stated as follows: bits selected for puncturing        should not be the ones corresponding to the heavy-weight, or        strong columns, i.e. columns containing large number of non-zero        elements, 1's in this particular case.    -   Bits selected for puncturing should be chosen such that they all        participate in as many parity check equations as possible.

Some of these trade-offs can be observed from FIG. 24 showing the frameerror probability 240 for various situations.

FIG. 25 illustrates the base parity check matrix 250 used for obtainingthe results in FIG. 24. The codeword size is 1728, which is obtained byexpanding the base parity check matrix by the factor of z=72.

In FIG. 24, the curves are shown for six examples,

-   -   241: Shortened=0 Punctured=216 Infobits 3 strong columns    -   242: Shortened=0 Punctured=216 Infobits 3 weak columns    -   243: Shortened=0 Punctured=216 Infobits random    -   244: Shortened=0 Punctured=216 Parity columns 22, 23, 24    -   245: Shortened=0 Punctured=216 Parity random and    -   246: Shortened=0 Punctured=216 Parity columns 20, 22, 24

It can be seen from the FIG. 24 that puncturing bits corresponding toheavy-weight, or strong columns has a catastrophic effect on performance(241). On the other hand, puncturing block columns that do notparticipate in very many parity check equations does not provide verygood performance (244) either. The best results are obtained when bothcriteria are taken into account represented by curves 242, 243, 245,246. Among all of those, it appears that for the particular matrixstructure (irregular H_(d) part with the modified dual diagonal in theH_(p) part) the best results were obtained when the punctured bits wereselected from those corresponding to the weak columns of the data partof the parity check matrix, H_(d), (242). If the parity check matrix isarranged as in 221 of FIG. 22, then the puncturing bits can be selectedby starting from the leftmost bit of H_(d) and continuing withconsecutive bits towards the parity portion of the matrix.

The matrix in FIG. 25 has undergone column rearrangement such that allthe light-weight data columns have been put in the puncturing zone, i.e.leftmost part of the H_(d) part of the parity check matrix.

As discussed previously, in the case where the preservation of the exactcode rate is not mandatory, the shortening-to-puncturing ratio can bechosen such that it guarantees preservation of the performance level ofthe original code.

Normalizing the shortening-to-puncturing ratio, q, as follows:q_(normalized)=(N_(shortened)/N_(punctured))/[R/(1−R)],

means that q becomes independent of the code rate, R. Therefore,q_(normalized)=1, corresponds to the rate preserving case of combinedshortening and puncturing. However, if the goal is to preserveperformance, this normalized ratio must be greater than one:q_(normalized)>1. It was found through much experimentation that one:q_(normalized) in the range of 1.2-1.5 complies with the performancepreserving requirements.

In the case of a column regular parity check matrix, or more generally,approximately regular, or regular and approximately regular only in thedata part of the matrix, H_(d) the method described above in accordancewith one embodiment of the present invention is still preferred comparedto the existing random or periodic/random approach since the presentinvention ensures approximately constant row weight, which providesanother advantage from both the performance and the implementationcomplexity standpoints.

A large percentage of punctured bits paralyzes the iterative softdecision decoder. In the case of LDPC codes this is true even ifpuncturing is combined with some other operation such as shortening orextending the code. One could conclude this by studying the matrix 250of FIG. 25. Here, it can be seen that as puncturing progresses it ismore and more likely that a heavy weight column will be hit. This isundesirable and has a negative effect on the code performance. Definingthe puncturing percentage as:P_(puncture)=100×(N_(puncture)/M),

then it can be seen that the matrix 250 from FIG. 25 cannot toleratepuncturing in excess of P_(puncture_max)=33.3%. Therefore, thisparameter P_(puncture_max) must be set and taken into account whenperforming the combined shortening and puncturing operation.

Some of the embodiments of the present invention may include thefollowing characteristics:

-   -   Shortening, or combined shortening and puncturing is applied in        order to provide a large range of codeword sizes from a single        parity check matrix.    -   The effective code rate of the code defined by the parity check        matrix modified by shortening and puncturing is equal to or less        than the original code rate.    -   Shortening is performed so that the column weight distribution        of the modified matrix is optimal for the new matrix size and        code rate. Another solution is to keep the column weight        distribution of the new matrix only approximately optimum.    -   Shortening is performed so that the approximately uniform row        weight is preserved.    -   Puncturing is performed so that each of the bits selected for        puncturing is connected to as few check nodes as possible.    -   Puncturing is performed so that the bits selected for puncturing        all participate in as many parity check equations as possible.    -   Puncturing is performed so that the approximately uniform row        weight is preserved.    -   A suboptimal but computationally efficient method is to first        rearrange the columns of the data portion of the parity check        matrix, H_(d), by applying the preceding rules assuming that        shortening is applied to a group of consecutive bits of the data        portion of the parity check matrix and puncturing is applied to        another group of consecutive bits of the data portion of the        parity check matrix as illustrated by the example matrix 250        shown in FIG. 25.    -   Performance of the new code, which is obtained by applying both        the shortening and puncturing, can be kept at the level of the        original code by setting the normalized shortening to puncturing        ratio, q_(normalized)=(N_(shortened)/N_(punctured))/[R/(1−R)]        greater than one. The q_(normalized) value depends on the        particular matrix design and the code rate, R. When the        preservation of the original code rate is required, the        normalized shortening to puncturing ratio shall be set to one        (q_(normalized)=1).    -   The amount of puncturing is limited to a certain value, which        depends on the particular parity check matrix design.

The system, apparatus, and method as described above are preferablycombined with one or more matrices shown in the FIGS. 26a, 26b and 26cthat have been selected as being particularly suited to the methodology.They may be used alone, or with other embodiments of the presentinvention.

The matrices in FIGS. 26a, 26b and 26c have been derived and tested, andhave proven to be at least as efficient as prior art matrices incorrecting errors.

A first group of matrices (FIG. 26a #1-#5) cover expansion factors up to72 using rates R=½, ⅔, ¾, ⅚, and ⅞, respectively. The matrices may beutilized as they are specified or with the columns in the data portionof any of the matrices (first R*24 columns on the left side) reorderedin anyway. The parity portion ((1−R)*24 rightmost columns) of thematrices is designed to allow simple encoding algorithms. They may beused in standards, such as wireless standards IEEE 802.11, and IEEE802.16.

A further matrix (FIG. 26b #6) covers expansion factors up to 96 forrate R=¾. The matrix may be utilized as it is or with the columns in thedata portion (first R*24 columns on the left side) reordered in any way.The parity portion ((1−R)*24 rightmost columns) of the matrix isdesigned to allow simple encoding algorithms.

The rate R=¾ matrices (FIG. 26b #7-#9) cover expansion factors in therange between 24 and 96 in increments of 4.

The rate R=⅚ matrix (FIG. 26b #10) may be used to cover expansionfactors in the range between 24 and 96 in increments of 4.

The two rate R=⅚ matrices (FIGS. 26c #11 and #12) cover expansionfactors up to L_(max)=96. The matrices may be utilized as they are orwith the columns in the data portion (first R*24 columns on the leftside) reordered in any way. The parity portion ((1−R)*24 rightmostcolumns) of the matrix is designed to allow simple encoding algorithms.These particular matrices can accommodate codeword sizes in the range576 to 2304 in increments of 96. Consequently, the expansion factors, Lare in the range 24 to 96 in increments of 4. Right circular shifts ofthe corresponding L×L identity matrix (as explained in the previoussection), s′, are determined as follows:s′=floor{s. (L/96)},

where s is the right circular shift corresponding to the maximumcodeword size (for L=Lmax=96), and it is specified in the matrixdefinitions.

The invention can be implemented in digital electronic circuitry, or incomputer hardware, firmware, software, or in combinations thereof.Apparatus of the invention can be implemented in a computer programproduct tangibly embodied in a machine-readable storage device forexecution by a programmable processor; and method actions can beperformed by a programmable processor executing a program ofinstructions to perform functions of the invention by operating on inputdata and generating output. The invention can be implementedadvantageously in one or more computer programs that are executable on aprogrammable system including at least one programmable processorcoupled to receive data and instructions from, and to transmit data andinstructions to, a data storage system, at least one input device, andat least one output device. Each computer program can be implemented ina high-level procedural or object oriented programming language, or inassembly or machine language if desired; and in any case, the languagecan be a compiled or interpreted language. Suitable processors include,by way of example, both general and special purpose microprocessors.Generally, a processor will receive instructions and data from aread-only memory and/or a random access memory. Generally, a computerwill include one or more mass storage devices for storing data files.Storage devices suitable for tangibly embodying computer programinstructions and data include all forms of non-volatile memory,including by way of example semiconductor memory devices, such as EPROM,EEPROM, and flash memory devices; magnetic disks such as internal harddisks and removable disks; magneto-optical disks; and CD-ROM disks. Anyof the foregoing can be supplemented by, or incorporated in, ASICs(application-specific integrated circuits). Further, a computer datasignal representing the software code which may be embedded in a carrierwave may be transmitted via a communication network. Such a computerreadable memory and a computer data signal are also within the scope ofthe present invention, as well as the hardware, software and thecombination thereof.

While particular embodiments of the present invention have been shownand described, changes and modifications may be made to such embodimentswithout departing from the true scope of the invention.

What is claimed is:
 1. A method of low-density parity-check (LDPC)encoding data, comprising: receiving input data from a data source; andapplying the following expanded parity check matrix to the input data togenerate encoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86 −1 62 94 19 84−1 95 78 −1 15 −1 −1 92 71 −1 55 −1 12 66 45 79 −1 78 −1 −1 38 61 −1 66 9 73 47 64 −1 39 61 43 −1 −1 −1 −1 32 52 55 80 95 22  6 51 −1 63 31 8820 −1 −1 −1  6 40 66 16 37 38  4 11 −1 46 48  0 −1 −1 −1 −1 −1 45 24 3230 −1 −1  0  0 −1 −1 −1 10 −1 22 55 70 82 −1 −1  0  0 −1 −1 −1 −1 −1 −195 32  0 −1 −1  0  0 −1 24 90 44 20 −1 −1 −1 −1 −1 −1  0  0 71 53 −1 −127 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96).
 2. A method of decoding low-density parity-check(LDPC) encoded data, comprising: receiving encoded data from a datasource; and applying the following expanded parity check matrix to theencoded data to generate decoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86−1 37 38  4 11 −1 46 48  0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −192 −1 45 24 32 30 −1 −1  0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1−1 10 −1 22 55 70 82 −1 −1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 6143 −1 −1 −1 −1 95 32  0 −1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  651 24 90 44 20 −1 −1 −1 −1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 6616 71 53 −1 −1 27 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96).
 3. Apparatus for low-density parity-check (LDPC)encoding data, comprising: an input port operable to receive input datafrom a data source; and circuitry coupled to the input port and operableto apply the following expanded parity check matrix to the input data togenerate encoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86 −1 37 38  4 11−1 46 48  0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −1 92 −1 45 24 3230 −1 −1  0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1 −1 10 −1 22 5570 82 −1 −1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 61 43 −1 −1 −1 −195 32  0 −1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  6 51 24 90 44 20−1 −1 −1 −1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 66 16 71 53 −1 −127 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96).
 4. Apparatus for low-density parity-check (LDPC)encoding data, comprising: an input port operable to receive input datafrom a data source; and a matrix application element operable to applythe following expanded parity check matrix to the input data to generateencoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86 −1 37 38  4 11 −1 46 48 0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −1 92 −1 45 24 32 30 −1 −1 0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1 −1 10 −1 22 55 70 82 −1−1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 61 43 −1 −1 −1 −1 95 32  0−1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  6 51 24 90 44 20 −1 −1 −1−1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 66 16 71 53 −1 −1 27 26 48−1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96).
 5. Apparatus for low-density parity-check (LDPC)encoding data, comprising: an input port operable to receive input datafrom a data source; and means for applying the following expanded paritycheck matrix to the input data to generate encoded data:  6 38  3 93 −1−1 −1 30 70 −1 86 −1 37 38  4 11 −1 46 48  0 −1 −1 −1 −1 62 94 19 84 −195 78 −1 15 −1 −1 92 −1 45 24 32 30 −1 −1  0  0 −1 −1 −1 71 −1 55 −1 1266 45 79 −1 78 −1 −1 10 −1 22 55 70 82 −1 −1  0  0 −1 −1 38 61 −1 66  973 47 64 −1 39 61 43 −1 −1 −1 −1 95 32  0 −1 −1  0  0 −1 −1 −1 −1 −1 3252 55 80 95 22  6 51 24 90 44 20 −1 −1 −1 −1 −1 −1  0  0 −1 63 31 88 20−1 −1 −1  6 40 66 16 71 53 −1 −1 27 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96).
 6. Apparatus for decoding low-density parity-check(LDPC) encoded data, comprising: an input port operable to receiveencoded data from a data source; and circuitry coupled to the input portand operable to apply the following expanded parity check matrix to theencoded data to generate decoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86−1 37 38  4 11 −1 46 48  0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −192 −1 45 24 32 30 −1 −1  0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1−1 10 −1 22 55 70 82 −1 −1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 6143 −1 −1 −1 −1 95 32  0 −1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  651 24 90 44 20 −1 −1 −1 −1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 6616 71 53 −1 −1 27 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96).
 7. Apparatus for decoding low-density parity-check(LDPC) encoded data, comprising: an input port operable to receiveencoded data from a data source; and a matrix application elementoperable to apply the following expanded parity check matrix to theencoded data to generate decoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86−1 37 38  4 11 −1 46 48  0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −192 −1 45 24 32 30 −1 −1  0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1−1 10 −1 22 55 70 82 −1 −1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 6143 −1 −1 −1 −1 95 32  0 −1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  651 24 90 44 20 −1 −1 −1 −1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 6616 71 53 −1 −1 27 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96).
 8. Apparatus for decoding low-density parity-check(LDPC) encoded data, comprising: an input port operable to receiveencoded data from a data source; and means for applying the followingexpanded parity check matrix to the encoded data to generate decodeddata:  6 38  3 93 −1 −1 −1 30 70 −1 86 −1 37 38  4 11 −1 46 48  0 −1 −1−1 −1 62 94 19 84 −1 95 78 −1 15 −1 −1 92 −1 45 24 32 30 −1 −1  0  0 −1−1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1 −1 10 −1 22 55 70 82 −1 −1  0  0−1 −1 38 61 −1 66  9 73 47 64 −1 39 61 43 −1 −1 −1 −1 95 32  0 −1 −1  0 0 −1 −1 −1 −1 −1 32 52 55 80 95 22  6 51 24 90 44 20 −1 −1 −1 −1 −1 −1 0  0 −1 63 31 88 20 −1 −1 −1  6 40 66 16 71 53 −1 −1 27 26 48 −1 −1 −1−1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96).
 9. A telecommunications network, comprising: an LDPCencoder operable to apply the following expanded parity check matrix toinput data to generate encoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86 −137 38  4 11 −1 46 48  0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −1 92−1 45 24 32 30 −1 −1  0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1 −110 −1 22 55 70 82 −1 −1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 61 43−1 −1 −1 −1 95 32  0 −1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  6 5124 90 44 20 −1 −1 −1 −1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 66 1671 53 −1 −1 27 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96); a transmitter operable to transmit the encoded dataover a transmission medium; a receiver operable to receive thetransmitted encoded data; and an LDPC decoder operable to apply saidexpanded parity check matrix to the encoded data to recover the inputdata.
 10. A method of operating a telecommunications network,comprising: applying the following expanded parity check matrix to inputdata to generate encoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86 −1 37 38 4 11 −1 46 48  0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −1 92 −1 4524 32 30 −1 −1  0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1 −1 10 −122 55 70 82 −1 −1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 61 43 −1 −1−1 −1 95 32  0 −1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  6 51 24 9044 20 −1 −1 −1 −1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 66 16 71 53−1 −1 27 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96); transmitting the encoded data over a transmissionmedium; receiving the transmitted encoded data; and applying saidexpanded parity check matrix to the encoded data to recover the inputdata.
 11. A transceiver, comprising: an LDPC encoder operable to applythe following expanded parity check matrix to input data to generateencoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86 −1 37 38  4 11 −1 46 48 0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −1 92 −1 45 24 32 30 −1 −1 0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1 −1 10 −1 22 55 70 82 −1−1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 61 43 −1 −1 −1 −1 95 32  0−1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  6 51 24 90 44 20 −1 −1 −1−1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 66 16 71 53 −1 −1 27 26 48−1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96); a transmitter operable to transmit the encoded dataover a transmission medium; a receiver operable to receive encoded datafrom the transmission medium; and an LDPC decoder operable to apply saidexpanded parity check matrix to the received encoded data to generatedecoded data.
 12. A method of operating a transceiver, comprising:applying the following expanded parity check matrix to input data togenerate encoded data:  6 38  3 93 −1 −1 −1 30 70 −1 86 −1 37 38  4 11−1 46 48  0 −1 −1 −1 −1 62 94 19 84 −1 95 78 −1 15 −1 −1 92 −1 45 24 3230 −1 −1  0  0 −1 −1 −1 71 −1 55 −1 12 66 45 79 −1 78 −1 −1 10 −1 22 5570 82 −1 −1  0  0 −1 −1 38 61 −1 66  9 73 47 64 −1 39 61 43 −1 −1 −1 −195 32  0 −1 −1  0  0 −1 −1 −1 −1 −1 32 52 55 80 95 22  6 51 24 90 44 20−1 −1 −1 −1 −1 −1  0  0 −1 63 31 88 20 −1 −1 −1  6 40 66 16 71 53 −1 −127 26 48 −1 −1 −1 −1  0

wherein an expansion factor, L, is between 24 and 96, −1 represents anL×L all-zero square matrix, and any other integer, Sij, represents anL×L identity matrix circularly right shifted by a shift amount equal tofloor ((L×Sij)/96); transmitting the encoded data over a transmissionmedium; receiving encoded data from the transmission medium; andapplying said expanded parity check matrix to the received encoded datato generate decoded data.
 13. A method to operate a wireless device toencode data using low-density parity-check (LDPC) encoding, the methodcomprising: computing a number of modulated orthogonalfrequency-division multiplexing (OFDM) symbols for transmitting thedata; computing a number of shortening bits N_(shortened) for at leastone LDPC codeword to be used during an encoding; distributing the numberof shortening bits N_(shortened) over the at least one LDPC codeword;computing a number of puncturing bits N_(punctured) for the at least oneLDPC codeword; distributing the number of puncturing bits over the atleast one LDPC codeword; determining a criterion using at least one ofthe number of shortening bits N_(shortened) and the number of puncturingbits N_(punctured); if the criterion is met, increasing the number ofmodulated OFDM symbols and recalculating the number of puncturing bitsN_(punctured); generating the encoded data using the number ofshortening bits N_(shortened), the number of puncturing bitsN_(punctured), and the at least one LDPC codeword, wherein shortening isperformed by setting N_(shortened) information bits to 0 within the atleast one LDPC codeword, and puncturing is performed by discardingN_(punctured) parity bits from the at least one LDPC codeword; andtransmitting the encoded data.
 14. The method of claim 13, wherein thecriterion is determined using both the number of shortening bitsN_(shortened) and the number of puncturing bits N_(punctured).
 15. Themethod of claim 13, further comprising computing a number of the atleast one LDPC codeword to encode the data and a length of each of theat least one LDPC codeword.
 16. The method of claim 13, whereintransmitting the encoded data comprises transmitting the encoded datausing the number of modulated OFDM symbols.
 17. A wireless devicecomprising: a low-density parity-check (LDPC) encoder circuit configuredto: compute a number of modulated orthogonal frequency-divisionmultiplexing (OFDM) symbols for transmitting data; compute a number ofshortening bits N_(shortened) for at least one LDPC codeword to be usedduring an encoding; distribute the number of shortening bitsN_(shortened) over the at least one LDPC codeword; compute a number ofpuncturing bits N_(punctured) for the at least one LDPC codeword;distribute the number of puncturing bits over the at least one LDPCcodeword; determine a criterion using at least one of the number ofshortening bits N_(shortened) and the number of puncturing bitsN_(punctured); if the criterion is met, increase the number of modulatedOFDM symbols and recalculate the number of puncturing bitsN_(punctured); and generate the encoded data using the number ofshortening bits N_(shortened), the number of puncturing bitsN_(punctured), and the at least one LDPC codeword, wherein shortening isperformed by setting N_(shortened) information bits to 0 within the atleast one LDPC codeword, and puncturing is performed by discardingN_(punctured) parity bits from the at least one LDPC codeword; and atransmitter configured to transmit the encoded data.
 18. The wirelessdevice of claim 17, wherein the criterion is determined using both thenumber of shortening bits N_(shortened) and the number of puncturingbits N_(punctured).
 19. The wireless device of claim 17, wherein theLDPC encoder circuit is further configured to compute a number of the atleast one LDPC codeword to encode the data and a length of each of theat least one LDPC codeword.
 20. The wireless device of claim 17, whereinthe transmitter is configured to transmit the encoded data using thenumber of modulated OFDM symbols.
 21. A non-transitory computer readablemedium comprising instructions that when executed by a wireless devicecause the wireless device to perform steps of a method to encode datausing low-density parity-check (LDPC) encoding, the method comprising:computing a number of modulated orthogonal frequency-divisionmultiplexing (OFDM) symbols for transmitting the data; computing anumber of shortening bits N_(shortened) for at least one LDPC codewordto be used during an encoding; distributing the number of shorteningbits N_(shortened) over the at least one LDPC codeword; computing anumber of puncturing bits N_(punctured) for the at least one LDPCcodeword; distributing the number of puncturing bits over the at leastone LDPC codeword; determining a criterion using at least one of thenumber of shortening bits N_(shortened) and the number of puncturingbits N_(punctured); if the criterion is met, increasing the number ofmodulated OFDM symbols and recalculating the number of puncturing bitsN_(punctured); generating the encoded data using the number ofshortening bits N_(shortened), the number of puncturing bitsN_(punctured), and the at least one LDPC codeword, wherein shortening isperformed by setting N_(shortened) information bits to 0 within the atleast one LDPC codeword, and puncturing is performed by discardingN_(punctured) parity bits from the at least one LDPC codeword; andtransmitting the encoded data.
 22. The non-transitory computer readablemedium of claim 21, wherein the criterion is determined using both thenumber of shortening bits N_(shortened) and the number of puncturingbits N_(punctured).
 23. The non-transitory computer readable medium ofclaim 21, wherein the method further comprises computing a number of theat least one LDPC codeword to encode the data and a length of each ofthe at least one LDPC codeword.
 24. The non-transitory computer readablemedium of claim 21, wherein transmitting the encoded data comprisestransmitting the encoded data using the number of modulated OFDMsymbols.